Please direct your responses to: https://sjobs.brassring.com/1033/ASP/TG/cim_jobdetail.asp?partnerid=11730&siteid=111&AReq=9746BR&Codes=IJB
In this position, the individual will be responsible for developing and preparing multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. May check design layouts and detailed drawings.
This position requires a BS/BA degree or equivalent with 8 or more years of related experience. Excellent understanding of flash memory layout and its hierarchy. Ability to understand and build flash memory arrays. Requires detail exposure experience with laying out pitch circuits. Should have strong skills in floor-planning and manual routing; understand the routing and placement requirements based on schematics. Experience in planning and routing power bus and full chip routing. Experience with at least one chip from start to tape-out. Lead test chip project. Excellent analog layout skill. Focus on analog layout placement matching and routing. Focus on charge pump, voltage generator. Experience in understanding parasitics and its impact to layout. Ability to optimize critical paths. Lead test chip project. Co-lead derivate project. Develop cell-level, block-level, and full chip level DRC/LVS. Excellent performing manual routing and semi-auto routing. Responsible optimization of various blocks including routing and via optimization. Responsible full chip activities including tape-out and ECO's after initial tape-out. Responsible test structure development including structures necessary for design rule development. Responsible of I/O circuits layout, ESD circuits layout, and pad layout. Good understanding of flash memory layout and its hierarchy. Be proficient in understanding layout and schematic hierarchy of existing chips and be able to make changes to existing chips and be able to at least take ownership of parts of the full chip. Work as part of a physical design team. Work closely with layout manager & layout project lead. Good understand fundamental process steps. Work with design engineer for layout requirements. Independent thinking on assignment and able to come up with floor plan to optimize block placement and routing. Experience with Cadence "VLE, VXL, CCAR, PCELL" layout and schematic tools. Experience in Hercules/Calibre DRC/LVS verification tools. Experience in UNIX environment. Needs to be able to debug DRC/LVS independently. Must be proficient in post layout processing, preferably using Hercules tool set and be able to learn and understand design rules very quickly. Fast learner. Detail oriented. Excellent communication. Team oriented person. Good layout and layout planning skills and be able to provide quality layout without much supervision.
SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401 (K), comprehensive insurance and tuition reimbursement. SanDisk is an equal opportunity employer.
For more information, please contact Tina Campbell at tina.campbell@sandisk.com
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