Please direct your responses to: arexinger@nvidia.com
SENIOR MEMORY CONTROLLER VERIFICATION ENGINEER
As a Verification Engineer at NVIDIA, you will verify the design and implementation of the industry's leading mobile microprocessor. In this position, you will be responsible for verification of memory subsystem design, architecture, golden models and micro-architecture using advanced verification methodologies. Design or verification experience of dynamic memory controllers (ddr2, 3, 4, lpddr2, 3) plus extensive experience with interface characterization post silicon is a must. You are expected to lead a verification team, mentor junior verification engineers, understand the design and implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, verify correctness of the design. You will be working with architects, designers, emulation and silicon verification teams to accomplish your tasks.
MINIMUM REQUIREMENTS:
- BS / MS with 8+ years of experience.
- Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
- Experience in architecting test bench environments for unit level verification.
- Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
- C++ programming language experience.
- Expertise in System Verilog.
- Scripting knowledge.
- Knowledge of 3/4/2/3 protocols.
- Good debugging and problem solving skills.
- Good communication skills and ability desire to work as a team player are a must.
We are an AA/EEO/Veterans/Disabled employer
SENIOR MEMORY CONTROLLER VERIFICATION ENGINEER
As a Verification Engineer at NVIDIA, you will verify the design and implementation of the industry's leading mobile microprocessor. In this position, you will be responsible for verification of memory subsystem design, architecture, golden models and micro-architecture using advanced verification methodologies. Design or verification experience of dynamic memory controllers (ddr2, 3, 4, lpddr2, 3) plus extensive experience with interface characterization post silicon is a must. You are expected to lead a verification team, mentor junior verification engineers, understand the design and implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, verify correctness of the design. You will be working with architects, designers, emulation and silicon verification teams to accomplish your tasks.
MINIMUM REQUIREMENTS:
- BS / MS with 8+ years of experience.
- Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
- Experience in architecting test bench environments for unit level verification.
- Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
- C++ programming language experience.
- Expertise in System Verilog.
- Scripting knowledge.
- Knowledge of 3/4/2/3 protocols.
- Good debugging and problem solving skills.
- Good communication skills and ability desire to work as a team player are a must.
We are an AA/EEO/Veterans/Disabled employer
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Posted by: KIT List Jobs <jobposting2@kitlist.org>
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