Cresta Partners, a leading executive search firm serving small to mid-size technology companies, is conducting a retained search for a Senior Analog Design Engineer for our client in the San Francisco Bay Area.
Our client (the Company) is a leader in driving the architecture and semiconductor implementations for the secure storage, distribution and presentation of high-definition content in the consumer electronics and personal computing markets. It is known for creating and driving industry standards for digital content delivery and leveraging partnerships with global leaders in CE and PC markets to meet the growing needs of consumers worldwide. It is a leading provider of proven semiconductor IP solutions for high definition multimedia and data storage applications.
Our client, based in Sunnyvale, California, has achieved rapid growth and yet continues to maintain the focus and working style of a startup. In addition to shipping over 130 million mixed-signal semiconductors, the Company is one of the world's top ten intellectual property suppliers. The Company is a recognized leader in HDMI audio/video, MPEG-2/H.264/VC-1 video codecs, Mobile Camera and SATA storage technologies. In 2010, the Company formed the Mobile High-Definition Link (MHL) Consortium with Nokia Corporation, Samsung Electronics, Sony Corporation and Toshiba Corporation. MHL is a new mobile HD interface standard which will drive new opportunities for HDTV, PC monitor, MFM, and HD projection devices.
Our client is seeking a strong Senior Analog Design Engineer who will work in the Company's Analog Advanced Tech Group. This group designs all the analog building blocks for the various products in the Company, especially those focusing on the analog cores for high-speed & low-power serial link technology, called SerDes (serializer / de-serializer) or transceiver or PHY (physical layer), for digital data transmission in PC, consumer electronics, storage, network, and memory applications. He/She will lead the technical development of high-performance stand-alone PHY, or combined PHY, to handle multiple-purpose serial link specifications per market requirements.
This highly technical challenging position requires extensive experience with architecture-definition/selection and detailed circuit design to facilitate high-speed (multi-gigabit per second) serial communication links: 3Gbps~10Gbps transceivers such as HDMI, SATA, PICe, USB3.0, and new wired serial link applications.
Job Requirements / Qualifications
MSEE with 6+ years or PhD with 3+ years on SerDes design and architecture
Requires design and successful product delivery experience on serial link technology (for example, HDMI, SATA, PCle, Displayport, XAUI, etc.) including support in layout and characterization and requires knowledge about the detailed electrical spec of serial links.
Requires knowledge/experience on system architecture and building blocks of serial link: PLL/DLL, CDR (clock-data-recovery), Equalizer, and Driver/Receiver
Must be familiar with high-speed analog design environment, including HSPICE/HSIM, and analog-digital co-simulation including AMS
Other Requirements: practical experience in designing solutions to market requirements, experience building modular designs that were used in different process technology, must have demonstrated engineering creativity to solve challenging technical design issues
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