Please direct your responses to: pplattaxiom@yahoo.com
Responsibilities: Major work will include to lead and provide signal integrity support for N7K and Apex networking products. The scope of work includes: System level simulation of high speed serial interfaces, including die, package and board; High bandwidth 3-D interconnect and channel modeling including solder balls, vias and connectors; Serdes test chip measurement and interoperability testing; Serdes tuning and link optimization on prototypes and system bring-up.Work with SI teammates on I/O selection/simulations, package pin assignment, package modeling, crosstalk analysis, power supply noise analysis, and EDA/lab tools evaluation and correlation. Required Qualifications:MSEE or PhD-EE with over 5 years of experience in signal integrityHands on experience on chip and system levels signal Integrity and power integrity analyses is a must.Familiarity with high-speed serial interfaces (SFI, XFI, KR, Fiber Channel, PCIe, CEI) channel design and signal integrity considerationTransmission line theory and microwave engineering concepts such as Maxwell's equations, S-parameter, etc.Knowledge on PCB stackup/construction, ASIC package stackup/construction.Familiar with simulation and modeling tools like Hspice, ADS, HFSS, PowerSI, Sentinel-PI, etc.Ability to use lab equipment for measurements like Oscilloscopes, VNA, Spectrum Analyzer, BertScope, etc.Ability to probe high bit rate signals and do power noise measurementsStrong written and oral communication, as well as documentation skills.Ability to be a self-starter, work independently and in teams Ability to use, understand and write scripts for system testing
Send your resume to pplattaxiom@yahoo.com for immediate review.
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