Senior SoC Verification Engineer
• Define and develop verification architecture, methodologies, protocols and environments
• Write verification specifications, verification plans and documentation
• Generate test benches and automatic regression plans
• Be responsible for verification architecture, simulations, verifications and debugging of circuit and logic designs (schematics, analog, RTL)
• Complete block-level verification and chip level verification
• Interface with cross-functional teams and collaborate in all verification related activities
Required Skills and Experience:
BSEE or MSEE (Preferred)
• Minimum of 8 years related silicon design or verification work experience
• Hands on full product cycle project experience architecting and executing verification projects using systemverilog and OVM
• Hands on coverage driven verification project experience
• Hands on assertion based verification project experience
• Experience writing verification plans as well as test bench development, simulation and debugging
• Knowledge of IC chip design, development flow, process, and methodology
• Knowledge of CMOS logic design, circuit design, circuit analysis and CMOS device operation and characteristics
• Proficient in HDL languages System Verilog, Verilog and VHDL
• Good knowledge of UNIX shell scripting, Perl and TCL scripting
• Proficiency in a UNIX environment and CAE/CAD tools such as schematic capture, simulation, design verification
• Good analytical and problem solving skills
Company is a leader in its space, working on leading edge technologies and products
Please send resume to zshuster@batnet.com
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