Wednesday, February 22, 2012

[KITlist-Tech] Signal Integrity Technical Leader (Silicon Valley, CA)

Please direct your responses to: cbuduri@cisco.com

Contact Chandra Buduri ( cbuduri@cisco.com )

Signal Integrity Technical Leader
Location: San Jose, CA

Opportunity Snapshot
In this role, you will have the opportunity to work in the hardware engineering team of SAVBU - Cisco´s latest acquisition in the Data Center space. We are looking for candidates who strive in a fast paced start-up like environment. You will be part of a dedicated team, open communications, empowerment, innovation, teamwork and customer success are the foundations of the team. Thus, you set your own limits for learning and achievements.
We are looking for a motivated Signal Integrity Engineer to contribute to the development of our next generation product.

http://www.cisco.com/en/US/products/ps10265/index.html

Job Requirements:

- Seven plus years of experience in signal integrity
- Hands on person who can do both simulations and lab measurements to validate the simulation results
- Familier with multi gigabit serial busses, including PCIe, XAUI, KR, XFI, and SFI
- Contribute to the signaling and interconnect technology selection
- Definition and simulation of high speed interconnects using simulation tools
- Familiar with simulation tools such as ADS, Hspice, SpectraQuest, and CST
- Assess timing, noise margin, crosstalk, signal loss and signal
integrity of all clocks and critical data signaling and develop noise and timing budgets.
- Has done validation of simulations results using TDR, Network Analyzer, Oscilloscopes and other lab equipments
- Familiar with package and board co-design methodology
- Has done Package and system level power integrity design methodology
- Backplane design experience and analog circuit knowledge are preferred
- Familiarity with high speed I/Os such as HSTL, SSTL, LVDS, LVPECL, and serial busses
- Familiar with Memory technologies such as DDR2 and DD3
- Ability of working effectively with other disciplines a must
- Excellent documentation, communication skills,
- Effective interaction with other engineering discipline skills a must
- Minimum of 7+ years of relative experience with MSEE, PHD preferred.

Contact Chandra Buduri ( cbuduri@cisco.com )


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